Publications

@inproceedings{moser2025,

  title = {{Greyhound: A Reconfigurable and Extensible RISC-V SoC and eFPGA on IHP SG13G2}},

  author = {Leo Moser and Meinhard Kissich and Tobias Scheipel and Marcel Baunach},

  doi = {10.1109/Austrochip67945.2025.11183709},

  isbn = {2689-8144},

  year  = {2025},

  booktitle = {Proceedings of the 33rd Austrochip Workshop on Microelectronics (Austrochip)},

  address = {Linz, Austria}

}

@inproceedings{scheipel2025:youshallnot,

  title = {{You Shall Not Stall: Achieving RISC-V On-Demand Runtime-Reconfiguration using SCAIE-V}},

  author = {Tobias Scheipel and Maximilian Ogris and Marcel Baunach},

  doi = {10.1109/DSD67783.2025.00049},

  year  = {2025},

  booktitle = {Proceedings of the 28th Euromicro Conference on Digital System Design (DSD)},

  pages = {292--299},

  address = {Salerno, Italy}

}

@inproceedings{manjunath2025,

  title = {{Queryable Microarchitecture Knowledge Base using Retrieval-Augmented Generation}},

  author = {Vignesh Manjunath and Jesus Pestana and Tobias Scheipel and Marcel Baunach},

  doi = {10.64552/wipiec.v11i1.95 },

  year  = {2025},

  booktitle = {Works in Progress in Embedded Computing Journal (WiPiEC): Special Issue on selected papers of Works in Progress Session within 28th Euromicro Conference on Digital System Design (DSD) and 51th Euromicro Conference Series on Software Engineering and Advanced Applications (SEAA)},

  volume = {11},

  pages = {43--46},

  address = {Salerno, Italy}

}

@inproceedings{scheipel2025:hades-v,

  title = {{Learning by Puzzling: A Modular Approach to RISC-V Processor Design Education}},

  author = {Tobias Scheipel and David Beikircher and Florian Riedl},

  doi = {10.13140/RG.2.2.22964.16006},

  year  = {2025},

  booktitle = {Proceedings of the RISC-V Summit Europe 2025},

  address = {Paris, France}

}

@inproceedings{manjunath2025:formal,

  title = {{Formal Modeling and Verification of Low-Level AUTOSAR OS Specifications: Towards Portability and Correctness}},

  author = {Vignesh Manjunath and Tobias Scheipel and Marcel Baunach},

  doi = {10.1145/3672608.3707867},

  year  = {2025},

  booktitle = {Proceedings of the 40th ACM/SIGAPP Symposium on Applied Computing (SAC)},

  pages = {2007--2016},

  address = {Catania, Italy}

}

@inproceedings{nagarajan2024:formal,

  title = {{Formal Specifications of Real-Time AUTOSAR-Compliant Operating Systems}},

  author = {Drona Nagarajan and Tobias Scheipel and Marcel Baunach},

  doi = {10.1145/3696355.3699706},

  year  = {2024},

  booktitle = {Proceedings of the 32nd International Conference on Real-Time Networks and Systems (RTNS)},

  pages = {187--196},

  address = {Porto, Portugal}

}

@inproceedings{kanics2024:oposom,

  title = {{opoSoM: A Modular Measurement Platform for Dynamic Power Consumption of SoCs}},

  author = {Kristóf Kanics and Meinhard Kissich and Gerhard Wirrer and Tobias Scheipel and Marcel Baunach},

  issn = {2980-7298},

  year  = {2024},

  booktitle = {Works in Progress in Embedded Computing Journal (WiPiEC): Special Issue on selected papers of Works in Progress Session within 27th Euromicro Conference on Digital System Design (DSD) and 50th Euromicro Conference Series on Software Engineering and Advanced Applications (SEAA)},

  volume = {10},

  issue = {2},

  pages = {9--12},

  address = {Paris, France}

}

@inproceedings{moser2024:fpga,

  title = {{Stitching FPGA Fabrics with FABulous and OpenLane 2}},

  author = {Leo Moser and Meinhard Kissich and Tobias Scheipel and Marcel Baunach},

  doi = {10.1145/3637543.3652874},

  year  = {2024},

  booktitle = {Proceedings of the 21st ACM International Conference on Computing Frontiers (CF) Workshops and Special Sessions},

  pages = {71--74},

  address = {Ischia, Italy}

}

@inproceedings{nagarajan2024:mhlp,

  title = {{Fair and Starvation-Free Spinlock for Real-Time AUTOSAR systems: M-HLP}},

  author = {Drona Nagarajan and Tobias Scheipel and Marcel Baunach},

  doi = {10.1145/3605098.3635922},

  year  = {2024},

  booktitle = {Proceedings of the 39th ACM/SIGAPP Symposium on Applied Computing (SAC)},

  pages = {436--445},

  address = {Ávila, Spain}

}

@inproceedings{kissich2023:attest,

  title = {{One Solution to Rule Them All: ATTEST as Unified Testing Solution for Programming Courses}},

  author = {Meinhard Kissich and Kristóf Kanics and Klaus Weinbauer and Tobias Scheipel and Marcel Baunach},

  doi = {10.18420/fgbs2023h-01},

  year  = {2023},

  booktitle = {Tagungsband des FG-BS Herbsttreffens},

  address = {Bamberg, Germany}

}

@inproceedings{scheipel2022:moreMCU,

  title = {{moreMCU: A Runtime-reconfigurable RISC-V Platform for Sustainable Embedded Systems}},

  author = {Tobias Scheipel and Florian Angermair and Marcel Baunach},

  doi = {10.1109/DSD57027.2022.00013},

  year  = {2022},

  booktitle = {Proceedings of the 25th Euromicro Conference on Digital System Design (DSD)},

  pages = {24--31},

  address = {Maspalomas, Spain}

}

@inproceedings{scheipel2022:smartOS,

  title = {{SmartOS: An OS Architecture for Sustainable Embedded Systems}},

  author = {Scheipel, Tobias and Batista Ribeiro, Leandro and Sagaster, Tim and Baunach, Marcel},

  doi = {10.18420/fgbs2022f-01},

  year  = {2022},

  booktitle = {Tagungsband des FG-BS Frühjahrstreffens},

  pages = {1--10},

  address = {Hamburg, Germany}

}

@inproceedings{scheipel2021:updates,

  title = {{A Hardware/Software Concept for Partial Logic Updates of Embedded Soft Processors at Runtime}},

  author = {Tobias Scheipel and Peter Brungs and Marcel Baunach},

  doi = {10.1109/DSD53832.2021.00040},

  year  = {2021},

  booktitle = {Proceedings of the 24th Euromicro Conference on Digital System Design (DSD)},

  pages = {199--207},

  address = {Palermo, Italy}

}

@inproceedings{sivashanmugam2021:conversion,

  title = {{A Conversion Concept for a Legacy Software Model towards AUTOSAR Compliance}},

  author = {Vimal Sivashanmugam and Tobias Scheipel and Marcel Baunach and Bhargav Adabala},

  year  = {2021},

  booktitle = {Proceedings of the 1st International Conference on Computing and Applied Engineering (ICCAE)},

  volume = {9},

  pages = {62--66},

  address = {Goa, India}

}

@inproceedings{scheipel2021:pgReQ,

  title = {{papagenoReQ: Generation of Embedded Systems from Application Code Requirements}},

  author = {Tobias Scheipel and Marcel Baunach},

  doi = {10.1109/ICECCE52056.2021.9514257},

  year  = {2021},

  booktitle = {Proceedings of the 3rd International Conference on Electrical, Communication, and Computer Engineering (ICECCE)},

  pages = {1--6},

  address = {Kuala Lumpur, Malaysia}

}

@inproceedings{scheipel2020:pgX,

  title = {{papagenoX: Generation of Electronics and Logic for Embedded Systems from Application Software}},

  author = {Tobias Scheipel and Marcel Baunach},

  doi = {10.5220/0009159701360141},

  issn = {2184-4380},

  year  = {2020},

  booktitle = {Proceedings of the 9th International Conference on Sensor Networks (SENSORNETS)},

  pages = {136--141},

  address = {Valetta, Malta}

}

@inproceedings{fiala2020:ase,

  title = {{FPGA-Based Debugging with Dynamic Signal Selection at Run-Time}},

  author = {Gernot Fiala and Tobias Scheipel and Werner Neuwirth and Marcel Baunach},

  year  = {2020},

  booktitle = {Proceedings of the 17th Workshop on Automotive Software Engineering (ASE)},

  address = {Klagenfurt, Austria}

}

@inproceedings{scheipel2019:pgPCB,

  title = {{papagenoPCB: An Automated Printed Circuit Board Generation Approach for Embedded Systems Prototyping}},

  author = {Tobias Scheipel and Marcel Baunach},

  year  = {2019},

  booktitle = {Proceedings of the 14th International Conference on Systems (ICONS)},

  pages = {20--25},

  address = {Valencia, Spain}

}

@inproceedings{scheipel2017:echtzeit,

  title = {{Einheit zur anwendungsbezogenen Leistungsmessung für die RISC-V-Architektur}},

  author = {Tobias Scheipel and Fabian Mauroner and Marcel Baunach},

  editor = {Wolfgang A. Halang and Herwig Unger},

  doi = {10.1007/978-3-662-55785-3_8},

  isbn = {978-3-662-55785-3},

  year  = {2017},

  booktitle = {Logistik und Echtzeit},

  pages = {69--78},

  address = {Boppard, Germany}

}

@inproceedings{scheipel2017:pmu,

  title = {{System-Aware Performance Monitoring Unit for RISC-V Architectures}},

  author = {Tobias Scheipel and Fabian Mauroner and Marcel Baunach},

  doi = {10.1109/DSD.2017.28},

  year  = {2017},

  booktitle = {Proceedings of the 20th Euromicro Conference on Digital System Design (DSD)},

  pages = {86--93},

  address = {Vienna, Austria}

}