Tobias P. Scheipel
I am a postdoctoral researcher and teacher at the Embedded Automotive Systems Group at the Institute of Technical Informatics, Graz University of Technology. I did my PhD under the supervision of Prof. Marcel Baunach. You can find my dissertation here.
I received my Bachelor’s and Master’s degrees (Dipl.-Ing.) in Information and Computer Engineering at Graz University of Technology in Austria.
Currently, my research focuses on flexible and runtime-reconfigurable FPGA-based microcontroller architectures for embedded systems based on RISC-V. This work involves hardware/software codesign strategies for both processor logic and operating systems.
Apart from my research, I teach students how a CPU works and how to create their own CPU.
Publications (12)
Advances in Dynamic and Reconfigurable Embedded Systems Design
Scheipel, T., 19 Dec 2022, 216 p.Research output: Thesis › Doctoral Thesis
moreMCU: A Runtime-reconfigurable RISC-V Platform for Sustainable Embedded Systems
Scheipel, T., Angermair, F. & Baunach, M. C., 31 Aug 2022, 25th Euromicro Conference on Digital System Design (DSD). Maspalomas, Spain: EUROMICRO, p. 24-31 8 p.Research output: Chapter in Book/Report/Conference proceeding › Conference paper › peer-review
SmartOS: An OS Architecture for Sustainable Embedded Systems
Scheipel, T. P., Batista Ribeiro, L., Sagaster, T. & Baunach, M. C., 17 Mar 2022, 2022 - Fruehjahrstreffen FG BS. Gesellschaft für Informatik , 10 p.Research output: Chapter in Book/Report/Conference proceeding › Conference paper › peer-review
A Conversion Concept for a Legacy Software Model towards AUTOSAR Compliance
Sivashanmugam, V., Scheipel, T. P., Baunach, M. C. & Adabala, B., 8 Aug 2021, 1st International Conference on Computing and Applied Engineering. IJCRT - International Journal of Creative Research Thoughts, Vol. 9. 5 p.Research output: Chapter in Book/Report/Conference proceeding › Conference paper › peer-review
A Hardware/Software Concept for Partial Logic Updates of Embedded Soft Processors at Runtime
Scheipel, T. P., Brungs, P. & Baunach, M. C., 1 Sep 2021, 24th Euromicro Conference on Digital System Design (DSD). Palermo, Italy: EUROMICRO, p. 199 9 p.Research output: Chapter in Book/Report/Conference proceeding › Conference paper › peer-review
papagenoReQ: Generation of Embedded Systems from Application Code Requirements
Scheipel, T. P. & Baunach, M. C., 12 Jun 2021, 2021 International Conference on Electrical, Communication and Computer Engineering (ICECCE) . IEEE XploreResearch output: Chapter in Book/Report/Conference proceeding › Conference paper › peer-review
FPGA-Based Debugging with Dynamic Signal Selection at Run-Time
Fiala, G., Scheipel, T. P., Neuwirth, W. & Baunach, M. C., 1 Jan 2020, 17th Workshop on Automotive Software Engineering (ASE 2020). 7 p. (CEUR Workshop Proceedings; vol. 2581).Research output: Chapter in Book/Report/Conference proceeding › Conference paper › peer-review
papagenoX: Generation of Electronics and Logic for Embedded Systems from Application Software
Scheipel, T. P. & Baunach, M. C., 28 Feb 2020, SENSORNETS 2020 - Proceedings of the 9th International Conference on Sensor Networks. Ansari, N., Ahrens, A. & Benavente-Peces, C. (eds.). INSTICC – Institute for Systems and Technologies of Information, Control and Communication, Vol. 1. p. 136-141 6 p. (SENSORNETS 2020 - Proceedings of the 9th International Conference on Sensor Networks).Research output: Chapter in Book/Report/Conference proceeding › Conference paper › peer-review
papagenoPCB: An Automated Printed Circuit Board Generation Approach for Embedded Systems Prototyping
Scheipel, T. P. & Baunach, M. C., 24 Mar 2019, ICONS 2019 - The Fourteenth International Conference on Systems. p. 20-25 6 p.Research output: Chapter in Book/Report/Conference proceeding › Conference paper › peer-review
Smart mobility of the future – a challenge for embedded automotive systems
Baunach, M. C., Martins Gomes, R., Malenko, M., Mauroner, F., Batista Ribeiro, L. & Scheipel, T. P., 27 Jun 2018, In: Elektrotechnik und Informationstechnik. p. 304-308 5 p., 135.Research output: Contribution to journal › Article › peer-review
Einheit zur anwendungsbezogenen Leistungsmessung für die RISC-V-Architektur
Scheipel, T. P., Mauroner, F. & Baunach, M. C., 2017, Logistik und Echtzeit. Springer Verlag, p. 69-78 (Informatik aktuell).Research output: Chapter in Book/Report/Conference proceeding › Conference paper › peer-review
System-Aware Performance Monitoring Unit for RISC-V Architectures
Scheipel, T. P., Mauroner, F. & Baunach, M. C., 31 Aug 2017, Proceedings of the 20th Euromicro Conference on Digital System Design (DSD).Research output: Chapter in Book/Report/Conference proceeding › Conference paper › peer-review
Education
2022: Doctoral studies (PhD) in Electrical Engineering/Information and Communications
Engineering from Graz University of Technology
2017: Dipl.-Ing. (equivalent to MSc) in Information and Computer Engineering
from Graz University of Technology
2015: BSc in Information and Computer Engineering
from Graz University of Technology
© 2023 by Tobias Scheipel, Graz, Austria