Tobias P. Scheipel

I am a postdoctoral researcher and teacher at the Embedded Architectures & Systems Group at the Institute of Technical Informatics, Graz University of Technology. I did my PhD under the supervision of Prof. Marcel Baunach. You can find my dissertation here.
I received my Bachelor’s and Master’s degrees (Dipl.-Ing.) in Information and Computer Engineering at Graz University of Technology in Austria.

Currently, my research focuses on flexible and runtime-reconfigurable FPGA-based microcontroller architectures for embedded systems based on RISC-V. This work involves hardware/software codesign strategies for both processor logic and operating systems.

Apart from my research, I teach students how a CPU works and how to create their own CPU.


Education

2022:  Doctoral studies (PhD) in Electrical Engineering/Information and Communications
Engineering from Graz University of Technology

2017:  Dipl.-Ing. (equivalent to MSc) in Information and Computer Engineering
from Graz University of Technology

2015:  BSc in Information and Computer Engineering
from Graz University of Technology


Publications

Meinhard Kissich; Kristóf Kanics; Klaus Weinbauer; Tobias Scheipel; Marcel Baunach

One Solution to Rule Them All: ATTEST as Unified Testing Solution for Programming Courses Proceedings Article

In: Tagungsband des FG-BS Herbsttreffens, 2023.

Links

Tobias Scheipel

Advances in Dynamic and Reconfigurable Embedded Systems Design PhD Thesis

Graz University of Technology, 2022.

Links

Tobias Scheipel; Florian Angermair; Marcel Baunach

moreMCU: A Runtime-reconfigurable RISC-V Platform for Sustainable Embedded Systems Proceedings Article

In: Proceedings of the 25th Euromicro Conference on Digital System Design (DSD), pp. 24–31, Euromicro IEEE, Maspalomas, Spain, 2022.

Links

Tobias Scheipel; Leandro Batista Ribeiro; Tim Sagaster; Marcel Baunach

SmartOS: An OS Architecture for Sustainable Embedded Systems Proceedings Article

In: Tagungsband des FG-BS Frühjahrstreffens, pp. 1–10, Gesellschaft für Informatik e.V., Hamburg, Germany, 2022.

Links

Tobias Scheipel; Peter Brungs; Marcel Baunach

A Hardware/Software Concept for Partial Logic Updates of Embedded Soft Processors at Runtime Proceedings Article

In: Proceedings of the 24th Euromicro Conference on Digital System Design (DSD), pp. 199–207, Euromicro IEEE, Palermo, Italy, 2021.

Links

Vimal Sivashanmugam; Tobias Scheipel; Marcel Baunach; Bhargav Adabala

A Conversion Concept for a Legacy Software Model towards AUTOSAR Compliance Proceedings Article

In: Proceedings of the 1st International Conference on Computing and Applied Engineering (ICCAE), IJCRT, Goa, India, 2021.

Tobias Scheipel; Marcel Baunach

papagenoReQ: Generation of Embedded Systems from Application Code Requirements Proceedings Article

In: Proceedings of the 3rd International Conference on Electrical, Communication, and Computer Engineering (ICECCE), pp. 1–6, IEEE, Kuala Lumpur, Malaysia, 2021.

Links

Gernot Fiala; Tobias Scheipel; Werner Neuwirth; Marcel Baunach

FPGA-Based Debugging with Dynamic Signal Selection at Run-Time Proceedings Article

In: Proceedings of the 17th Workshop on Automotive Software Engineering (ASE), RWTH Aachen, Klagenfurt, Austria, 2020.

Tobias Scheipel; Marcel Baunach

papagenoX: Generation of Electronics and Logic for Embedded Systems from Application Software Proceedings Article

In: Proceedings of the 9th International Conference on Sensor Networks (SENSORNETS), pp. 136–141, INSTICC SciTePress, Valetta, Malta, 2020, ISSN: 2184-4380.

Links

Tobias Scheipel; Marcel Baunach

Towards an Automated Printed Circuit Board Generation Concept for Embedded Systems Journal Article

In: International Journal on Advances in Systems and Measurements (SysMea), vol. 12, no. 3&4, pp. 236–246, 2019, ISSN: 1942-261x.

Tobias Scheipel; Marcel Baunach

papagenoPCB: An Automated Printed Circuit Board Generation Approach for Embedded Systems Prototyping Proceedings Article

In: Proceedings of the 14th International Conference on Systems (ICONS), pp. 20–25, IARIA Valencia, Spain, 2019.

Marcel Baunach; Renata Martins Gomes; Maja Malenko; Fabian Mauroner; Leandro Batista Ribeiro; Tobias Scheipel

Smart mobility of the future – a challenge for embedded automotive systems Journal Article

In: e & i Elektrotechnik und Informationstechnik, pp. 304–308, 2018, ISSN: 1613-7620.

Links

Tobias Scheipel; Fabian Mauroner; Marcel Baunach

Einheit zur anwendungsbezogenen Leistungsmessung für die RISC-V-Architektur Proceedings Article

In: Halang, Wolfgang A.; Unger, Herwig (Ed.): Logistik und Echtzeit, pp. 69–78, Springer Berlin Heidelberg, Boppard, Germany, 2017, ISBN: 978-3-662-55785-3.

Abstract

Tobias Scheipel; Fabian Mauroner; Marcel Baunach

System-Aware Performance Monitoring Unit for RISC-V Architectures Proceedings Article

In: Proceedings of the 20th Euromicro Conference on Digital System Design (DSD), pp. 86–93, Euromicro IEEE, Vienna, Austria, 2017.

Links