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Tenure Track unlocked.
Iโm happy to announce that Iโm starting as a ๐ง๐ฒ๐ป๐๐ฟ๐ฒ-๐ง๐ฟ๐ฎ๐ฐ๐ธ ๐๐๐๐ถ๐๐๐ฎ๐ป๐ ๐ฃ๐ฟ๐ผ๐ณ๐ฒ๐๐๐ผ๐ฟ ๐ผ๐ณ ๐ฅ๐ฒ๐ฐ๐ผ๐ป๐ณ๐ถ๐ด๐๐ฟ๐ฎ๐ฏ๐น๐ฒ ๐๐ผ๐บ๐ฝ๐๐๐ฒ๐ฟ ๐๐ฟ๐ฐ๐ต๐ถ๐๐ฒ๐ฐ๐๐๐ฟ๐ฒ๐ (๐ฅ๐๐) at Technische Universitรคt Graz. ๐
RCA is about making hardware as ๐ข๐ฅ๐ข๐ฑ๐ต๐ข๐ฃ๐ญ๐ฆ as software โ so systems can update, optimize, and sustain themselves over time.
What this means in practice is a combination of:
โข ๐๐บ๐ฏ๐ฒ๐ฑ๐ฑ๐ฒ๐ฑ ๐ฝ๐ฟ๐ผ๐ฐ๐ฒ๐๐๐ผ๐ฟ & ๐๐ช/๐ฆ๐ช ๐ฐ๐ผ-๐ฑ๐ฒ๐๐ถ๐ด๐ป: from microarchitectures and memory hierarchies to operating systems, runtimes, and RTL โ bridging algorithms to silicon.
โข ๐๐๐ป๐ฎ๐บ๐ถ๐ฐ ๐ฃ๐ฎ๐ฟ๐๐ถ๐ฎ๐น ๐ฅ๐ฒ๐ฐ๐ผ๐ป๐ณ๐ถ๐ด๐๐ฟ๐ฎ๐๐ถ๐ผ๐ป (๐๐ฃ๐ฅ): hardware that can change at runtime to fit the task.
โข ๐ฒ๐๐ฃ๐๐-๐ฒ๐ป๐ต๐ฎ๐ป๐ฐ๐ฒ๐ฑ ๐ฆ๐ผ๐๐: tightly-coupled designs where we add domain-specific (instruction) extensions to processors on demand, utilizing embedded FPGAs (eFPGAs).
โข ๐ฅ๐๐ฆ๐-๐ฉ & ๐ผ๐ฝ๐ฒ๐ป ๐ฒ๐ฐ๐ผ๐๐๐๐๐ฒ๐บ๐: open ISA, open tooling, and Open Educational Resources (OER) in teaching.
โข ๐๐-๐ฎ๐๐ด๐บ๐ฒ๐ป๐๐ฒ๐ฑ & ๐๐๐๐๐ฎ๐ถ๐ป๐ฎ๐ฏ๐น๐ฒ ๐ฑ๐ถ๐ด๐ถ๐๐ฎ๐น ๐๐๐๐๐ฒ๐บ ๐ฑ๐ฒ๐๐ถ๐ด๐ป: faster design cycles, lower resource usage, and longer device lifetimes โ ultimately reducing e-waste.In teaching, Iโll keep pushing ๐ต๐ฎ๐ป๐ฑ๐-๐ผ๐ป, ๐ฝ๐ฟ๐ผ๐ท๐ฒ๐ฐ๐-๐ฏ๐ฎ๐๐ฒ๐ฑ ๐น๐ฒ๐ฎ๐ฟ๐ป๐ถ๐ป๐ด โ from C and embedded systems to reconfigurable SoC design โ because the best way to learn systems is to build them.
Iโm grateful to all mentors, collaborators, and students whoโve shaped this journey. Looking ahead, Iโm excited to deepen our ties with the ๐น๐ผ๐ฐ๐ฎ๐น ๐๐ฒ๐บ๐ถ๐ฐ๐ผ๐ป๐ฑ๐๐ฐ๐๐ผ๐ฟ ๐ถ๐ป๐ฑ๐๐๐๐ฟ๐, grow open-source design flows (and add a few tapeouts into the mix!), and co-create impactful RCA research with industry and academic partners.
If youโre a ๐๐๐๐ฑ๐ฒ๐ป๐ curious about projects or theses, or an ๐ถ๐ป๐ฑ๐๐๐๐ฟ๐ ๐ผ๐ฟ ๐ฎ๐ฐ๐ฎ๐ฑ๐ฒ๐บ๐ถ๐ฐ ๐ฐ๐ผ๐น๐น๐ฒ๐ฎ๐ด๐๐ฒ interested in collaboration, letโs talk.
Read the original article on LinkedIn.
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A Special Christmas Gift: HaDes-V is Now Live!
The holiday season is here, and weโre thrilled to share an early present for students, educators, hardware enthusiasts, and the entire RISC-V International communityโHaDes-V, our Open Educational Resource (OER) for RISC-V microcontroller design, is now available!
What is HaDes-V?
HaDes-V is a practical lab experience that guides you step-by-step through building a modular, pipelined 32-bit RISC-V processor from scratch. Developed at Graz University of Technology by David Beikircher, Florian Riedl, and myself, HaDes-V makes processor design accessible and engaging.
Key features of HaDes-V:
- ๐ RISC-V processor architecture implementation using SystemVerilog.
- ๐ค Hardware/Software co-design with RISC-V Assembly and C.
- ๐งฉ A jigsaw puzzle-style implementation with pre-compiled golden references to help you progress step by step.
- โ๏ธ Real-world FPGA development using the Basys3 development board.
Inspired by the spirit of the RISC-V community, HaDes-V supports the growing open hardware movement, offering tools and knowledge to make processor design customizable and inclusive.
Whatโs Included?
HaDes-V provides everything you need to get started:
- ๐ A comprehensive instruction guide, available as a free PDF download: Instruction Guide (PDF).
- ๐ป An open-source code repository: GitHub Repository.
These resources are shared under the CC BY 4.0 International and MIT licenses, ensuring they are free and adaptable for all. More information here.
In addition, HaDes-V is featured in the official RISC-V Learn repository, showcasing its value to the broader RISC-V ecosystem.
Why Should You Try HaDes-V?
HaDes-V bridges the gap between theory and practice, offering an exciting opportunity to:
- Learn processor design fundamentals.
- Gain hands-on experience with hardware/software co-design.
- Build confidence in real-world FPGA development.
- Join the innovative world of open hardware.
Whether youโre a student, educator, or hardware enthusiast, HaDes-V is designed to inspire and empower.
Ready to Dive In?
Start your journey with HaDes-V today! Access the resources here:
- ๐ Instruction Guide (PDF)
- ๐ป GitHub Repository
- ๐ RISC-V Learn Repository
Feedback and contributions are warmly welcomed! For more details, contact us via the GitHub repository.
Share the Knowledge!
Know someone passionate about RISC-V, hardware design, or embedded systems? Share HaDes-V with them and help spread the joy of learning and innovation this holiday season! ๐๐
For more updates, check out our LinkedIn announcement.
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Embarking on my Open Educational Resources (OER) journey
I’m excited to share a new chapter in my teaching journey: the creation of Open Educational Resources (OER). As a lecturer at Graz University of Technology, I’ve always sought innovative ways to make complex topics accessible and engaging for studentsโparticularly those from Electrical Engineering and Information and Computer Engineering backgrounds. Now, I’m extending this mission beyond the classroom by contributing to the world of OER. I try to keep my OERs up to date on my OER page.
OERs are free and openly licensed educational materials that allow educators and learners to adapt, share, and build upon content. They represent a decisive shift toward more inclusive and flexible learning opportunities. By creating OERs, I hope to contribute resources that support my students and empower educators and learners worldwide.
This initiative will apply to all the courses I teach. The full list of courses is on my teaching page.
Stay tuned as I continue to expand this collection, and feel free to reach out if you have feedback or ideas. Let’s make learning accessible to allโtogether.
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Promotio sub auspiciis Praesidentis rei publicae
Durchaus mit etwas Stolz kann ich vermelden, dass ich am Freitag in Graz unter den Auspizien des Bundesprรคsidenten [1] zum Doktor der Technischen Wissenschaften promoviert wurde. Am Montag habe ich dann den Ehrenring in der Hofburg in Wien von Herrn Bundesprรคsidenten Van der Bellen รผberreicht bekommen habe.
Mein besonderer Dank gilt allen meinen Wegbegleitern sowie den Institutionen, die dafรผr Sorge getragen haben, dass sich das Ganze auch “ausgeht”: Danke an die HTL Braunau, an die Technische Universitรคt Graz, sowie an meinen Dissertationsbetreuer Marcel Baunach und den Zweitgutachter Steffen Reith.
Weiterfรผhrende Informationen und Bilder zu den Zeremonien in Graz und Wien finden sich auf meiner Homepage [2].
With some pride, I can announce that I was awarded my doctorate in Engineering Sciences on Friday in Graz under the auspices of the Federal President [1]. On Monday, Federal President Van der Bellen presented me with the Ring of Honor at the Hofburg in Vienna.
My special thanks go to all my companions and the institutions that made sure that the whole thing “worked out”: Thanks to the HTL Braunau, to the Graz University of Technology, as well as to my dissertation supervisor Marcel Baunach and the second assessor Steffen Reith.
My homepage has further information and pictures of the ceremonies in Graz and Vienna [2].
[1] https://de.wikipedia.org/wiki/Sub_auspiciis
[2] https://www.scheipel.com/subauspiciis
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HaDes-V Launch
We are thrilled to announce the kickoff of our newly designed, RISC-V-based Microcontroller Design, Lab!
This year marks the first iteration of the new format, where students will embark on a hands-on learning experience as they delve into implementing the all-new RISC-V-based HaDes-V architecture.
Special thanks to David Beikircher and Florian Riedl for implementing the course.
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Hello World
What is he actually doing here? We do not know, yet. But at least the blog section is activated now. Stay tuned!