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Tenure Track unlocked.
I’m happy to announce that I’m starting as a 𝗧𝗲𝗻𝘂𝗿𝗲-𝗧𝗿𝗮𝗰𝗸 𝗔𝘀𝘀𝗶𝘀𝘁𝗮𝗻𝘁 𝗣𝗿𝗼𝗳𝗲𝘀𝘀𝗼𝗿 𝗼𝗳 𝗥𝗲𝗰𝗼𝗻𝗳𝗶𝗴𝘂𝗿𝗮𝗯𝗹𝗲 𝗖𝗼𝗺𝗽𝘂𝘁𝗲𝗿 𝗔𝗿𝗰𝗵𝗶𝘁𝗲𝗰𝘁𝘂𝗿𝗲𝘀 (𝗥𝗖𝗔) at Technische Universität Graz. 🚀
RCA is about making hardware as 𝘢𝘥𝘢𝘱𝘵𝘢𝘣𝘭𝘦 as software – so systems can update, optimize, and sustain themselves over time.
What this means in practice is a combination of:
• 𝗘𝗺𝗯𝗲𝗱𝗱𝗲𝗱 𝗽𝗿𝗼𝗰𝗲𝘀𝘀𝗼𝗿 & 𝗛𝗪/𝗦𝗪 𝗰𝗼-𝗱𝗲𝘀𝗶𝗴𝗻: from microarchitectures and memory hierarchies to operating systems, runtimes, and RTL – bridging algorithms to silicon.
• 𝗗𝘆𝗻𝗮𝗺𝗶𝗰 𝗣𝗮𝗿𝘁𝗶𝗮𝗹 𝗥𝗲𝗰𝗼𝗻𝗳𝗶𝗴𝘂𝗿𝗮𝘁𝗶𝗼𝗻 (𝗗𝗣𝗥): hardware that can change at runtime to fit the task.
• 𝗲𝗙𝗣𝗚𝗔-𝗲𝗻𝗵𝗮𝗻𝗰𝗲𝗱 𝗦𝗼𝗖𝘀: tightly-coupled designs where we add domain-specific (instruction) extensions to processors on demand, utilizing embedded FPGAs (eFPGAs).
• 𝗥𝗜𝗦𝗖-𝗩 & 𝗼𝗽𝗲𝗻 𝗲𝗰𝗼𝘀𝘆𝘀𝘁𝗲𝗺𝘀: open ISA, open tooling, and Open Educational Resources (OER) in teaching.
• 𝗔𝗜-𝗮𝘂𝗴𝗺𝗲𝗻𝘁𝗲𝗱 & 𝘀𝘂𝘀𝘁𝗮𝗶𝗻𝗮𝗯𝗹𝗲 𝗱𝗶𝗴𝗶𝘁𝗮𝗹 𝘀𝘆𝘀𝘁𝗲𝗺 𝗱𝗲𝘀𝗶𝗴𝗻: faster design cycles, lower resource usage, and longer device lifetimes – ultimately reducing e-waste.In teaching, I’ll keep pushing 𝗵𝗮𝗻𝗱𝘀-𝗼𝗻, 𝗽𝗿𝗼𝗷𝗲𝗰𝘁-𝗯𝗮𝘀𝗲𝗱 𝗹𝗲𝗮𝗿𝗻𝗶𝗻𝗴 – from C and embedded systems to reconfigurable SoC design – because the best way to learn systems is to build them.
I’m grateful to all mentors, collaborators, and students who’ve shaped this journey. Looking ahead, I’m excited to deepen our ties with the 𝗹𝗼𝗰𝗮𝗹 𝘀𝗲𝗺𝗶𝗰𝗼𝗻𝗱𝘂𝗰𝘁𝗼𝗿 𝗶𝗻𝗱𝘂𝘀𝘁𝗿𝘆, grow open-source design flows (and add a few tapeouts into the mix!), and co-create impactful RCA research with industry and academic partners.
If you’re a 𝘀𝘁𝘂𝗱𝗲𝗻𝘁 curious about projects or theses, or an 𝗶𝗻𝗱𝘂𝘀𝘁𝗿𝘆 𝗼𝗿 𝗮𝗰𝗮𝗱𝗲𝗺𝗶𝗰 𝗰𝗼𝗹𝗹𝗲𝗮𝗴𝘂𝗲 interested in collaboration, let’s talk.
Read the original article on LinkedIn.
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A Special Christmas Gift: HaDes-V is Now Live!
The holiday season is here, and we’re thrilled to share an early present for students, educators, hardware enthusiasts, and the entire RISC-V International community—HaDes-V, our Open Educational Resource (OER) for RISC-V microcontroller design, is now available!
What is HaDes-V?
HaDes-V is a practical lab experience that guides you step-by-step through building a modular, pipelined 32-bit RISC-V processor from scratch. Developed at Graz University of Technology by David Beikircher, Florian Riedl, and myself, HaDes-V makes processor design accessible and engaging.
Key features of HaDes-V:
- 📐 RISC-V processor architecture implementation using SystemVerilog.
- 🤝 Hardware/Software co-design with RISC-V Assembly and C.
- 🧩 A jigsaw puzzle-style implementation with pre-compiled golden references to help you progress step by step.
- ⚙️ Real-world FPGA development using the Basys3 development board.
Inspired by the spirit of the RISC-V community, HaDes-V supports the growing open hardware movement, offering tools and knowledge to make processor design customizable and inclusive.
What’s Included?
HaDes-V provides everything you need to get started:
- 📖 A comprehensive instruction guide, available as a free PDF download: Instruction Guide (PDF).
- 💻 An open-source code repository: GitHub Repository.
These resources are shared under the CC BY 4.0 International and MIT licenses, ensuring they are free and adaptable for all. More information here.
In addition, HaDes-V is featured in the official RISC-V Learn repository, showcasing its value to the broader RISC-V ecosystem.
Why Should You Try HaDes-V?
HaDes-V bridges the gap between theory and practice, offering an exciting opportunity to:
- Learn processor design fundamentals.
- Gain hands-on experience with hardware/software co-design.
- Build confidence in real-world FPGA development.
- Join the innovative world of open hardware.
Whether you’re a student, educator, or hardware enthusiast, HaDes-V is designed to inspire and empower.
Ready to Dive In?
Start your journey with HaDes-V today! Access the resources here:
Feedback and contributions are warmly welcomed! For more details, contact us via the GitHub repository.
Share the Knowledge!
Know someone passionate about RISC-V, hardware design, or embedded systems? Share HaDes-V with them and help spread the joy of learning and innovation this holiday season! 🎄🚀
For more updates, check out our LinkedIn announcement.
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Embarking on my Open Educational Resources (OER) journey
I’m excited to share a new chapter in my teaching journey: the creation of Open Educational Resources (OER). As a lecturer at Graz University of Technology, I’ve always sought innovative ways to make complex topics accessible and engaging for students—particularly those from Electrical Engineering and Information and Computer Engineering backgrounds. Now, I’m extending this mission beyond the classroom by contributing to the world of OER. I try to keep my OERs up to date on my OER page.
OERs are free and openly licensed educational materials that allow educators and learners to adapt, share, and build upon content. They represent a decisive shift toward more inclusive and flexible learning opportunities. By creating OERs, I hope to contribute resources that support my students and empower educators and learners worldwide.
This initiative will apply to all the courses I teach. The full list of courses is on my teaching page.
Stay tuned as I continue to expand this collection, and feel free to reach out if you have feedback or ideas. Let’s make learning accessible to all—together.
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Promotio sub auspiciis Praesidentis rei publicae
Durchaus mit etwas Stolz kann ich vermelden, dass ich am Freitag in Graz unter den Auspizien des Bundespräsidenten [1] zum Doktor der Technischen Wissenschaften promoviert wurde. Am Montag habe ich dann den Ehrenring in der Hofburg in Wien von Herrn Bundespräsidenten Van der Bellen überreicht bekommen habe.
Mein besonderer Dank gilt allen meinen Wegbegleitern sowie den Institutionen, die dafür Sorge getragen haben, dass sich das Ganze auch “ausgeht”: Danke an die HTL Braunau, an die Technische Universität Graz, sowie an meinen Dissertationsbetreuer Marcel Baunach und den Zweitgutachter Steffen Reith.
Weiterführende Informationen und Bilder zu den Zeremonien in Graz und Wien finden sich auf meiner Homepage [2].
With some pride, I can announce that I was awarded my doctorate in Engineering Sciences on Friday in Graz under the auspices of the Federal President [1]. On Monday, Federal President Van der Bellen presented me with the Ring of Honor at the Hofburg in Vienna.
My special thanks go to all my companions and the institutions that made sure that the whole thing “worked out”: Thanks to the HTL Braunau, to the Graz University of Technology, as well as to my dissertation supervisor Marcel Baunach and the second assessor Steffen Reith.
My homepage has further information and pictures of the ceremonies in Graz and Vienna [2].
[1] https://de.wikipedia.org/wiki/Sub_auspiciis
[2] https://www.scheipel.com/subauspiciis
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HaDes-V Launch
We are thrilled to announce the kickoff of our newly designed, RISC-V-based Microcontroller Design, Lab!
This year marks the first iteration of the new format, where students will embark on a hands-on learning experience as they delve into implementing the all-new RISC-V-based HaDes-V architecture.
Special thanks to David Beikircher and Florian Riedl for implementing the course.
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Hello World
What is he actually doing here? We do not know, yet. But at least the blog section is activated now. Stay tuned!