A Special Christmas Gift: HaDes-V is Now Live!

The holiday season is here, and we’re thrilled to share an early present for students, educators, hardware enthusiasts, and the entire RISC-V International community—HaDes-V, our Open Educational Resource (OER) for RISC-V microcontroller design, is now available!


What is HaDes-V?

HaDes-V is a practical lab experience that guides you step-by-step through building a modular, pipelined 32-bit RISC-V processor from scratch. Developed at Graz University of Technology by David Beikircher, Florian Riedl, and myself, HaDes-V makes processor design accessible and engaging.

Key features of HaDes-V:

  • 📐 RISC-V processor architecture implementation using SystemVerilog.
  • 🤝 Hardware/Software co-design with RISC-V Assembly and C.
  • 🧩 A jigsaw puzzle-style implementation with pre-compiled golden references to help you progress step by step.
  • ⚙️ Real-world FPGA development using the Basys3 development board.

Inspired by the spirit of the RISC-V community, HaDes-V supports the growing open hardware movement, offering tools and knowledge to make processor design customizable and inclusive.


What’s Included?

HaDes-V provides everything you need to get started:

These resources are shared under the CC BY 4.0 International and MIT licenses, ensuring they are free and adaptable for all. More information here.

In addition, HaDes-V is featured in the official RISC-V Learn repository, showcasing its value to the broader RISC-V ecosystem.


Why Should You Try HaDes-V?

HaDes-V bridges the gap between theory and practice, offering an exciting opportunity to:

  • Learn processor design fundamentals.
  • Gain hands-on experience with hardware/software co-design.
  • Build confidence in real-world FPGA development.
  • Join the innovative world of open hardware.

Whether you’re a student, educator, or hardware enthusiast, HaDes-V is designed to inspire and empower.


Ready to Dive In?

Start your journey with HaDes-V today! Access the resources here:

Feedback and contributions are warmly welcomed! For more details, contact us via the GitHub repository.


Share the Knowledge!

Know someone passionate about RISC-V, hardware design, or embedded systems? Share HaDes-V with them and help spread the joy of learning and innovation this holiday season! 🎄🚀

For more updates, check out our LinkedIn announcement.

Tobias Scheipel

I am a postdoctoral researcher and teacher at the Embedded Architectures & Systems Group at the Institute of Technical Informatics, Graz University of Technology. I conducted my PhD under the supervision of Prof. Marcel Baunach and graduated sub auspiciis Praesidentis rei publicae. You can find my dissertation here.

My research focuses on flexible and runtime-reconfigurable FPGA-based microcontroller architectures for embedded systems based on RISC-V. This involves hardware/software codesign strategies for both processor logic and embedded operating systems.

Apart from my research, I teach students how a CPU works, how to program embedded systems, how to write scientific publications, and how to create their own CPU.