Join the World RISC-V Days – Graz Edition, an in-person event encouraging RISC-V community collaboration. This gathering invites students, educators, developers, and industry leaders for discussions and keynotes to explore and connect with emerging RISC-V communities worldwide. All week long, individual communities will celebrate the World RISC-V Days – and the Graz RISC-V Community will do so at its edition on Feb 24!
When? February 24th, 2pm – 5pm (details below)
Where? Lecture Hall HS i1, Inffeldgasse 18, 8010 Graz
📢 Register for free on the official RISC-V page:
https://community.riscv.org/e/mgh373/
Preliminary Program:
- 14:00 Introduction
- 14:10 – 15:30 Pitch Talks
- 15:30 – 17:00 Poster/Showcase Session and Networking
Confirmed speakers:
- Maja Malenko (CHERI Ambassador; Insights on current CHERI developments)
- Leo Moser (Greyhound: A Reconfigurable and Extensible RISC-V SoC and eFPGA on IHP SG13G2)
- Yuning Liang (DeepComputing; Past and Next 15 Years RISC-V Destiny and Progress from RVA23)
- Prof. Marcel Baunach (RISC-V @ Institute of Technical Informatics/EAS Group)
- Silicon Austria Labs (tba)
- Florian Riedl and Tobias Scheipel (HaDes-V: Learning RISC-V CPU Design by Puzzling)
- Lorenz Schumm (Benchmarking the Core, not the Compiler: LLVM Scheduling for the CV32E40P)
- NXP Semiconductors (NXP Engagement in RISC-V)
→ preliminary program subject to change
If you want to contribute (talk, poster, showcase), RSVP and message separately at: tobias.scheipel@tugraz.at