Iโm happy to announce that Iโm starting as a ๐ง๐ฒ๐ป๐๐ฟ๐ฒ-๐ง๐ฟ๐ฎ๐ฐ๐ธ ๐๐๐๐ถ๐๐๐ฎ๐ป๐ ๐ฃ๐ฟ๐ผ๐ณ๐ฒ๐๐๐ผ๐ฟ ๐ผ๐ณ ๐ฅ๐ฒ๐ฐ๐ผ๐ป๐ณ๐ถ๐ด๐๐ฟ๐ฎ๐ฏ๐น๐ฒ ๐๐ผ๐บ๐ฝ๐๐๐ฒ๐ฟ ๐๐ฟ๐ฐ๐ต๐ถ๐๐ฒ๐ฐ๐๐๐ฟ๐ฒ๐ (๐ฅ๐๐) at Technische Universitรคt Graz. ๐
RCA is about making hardware as ๐ข๐ฅ๐ข๐ฑ๐ต๐ข๐ฃ๐ญ๐ฆ as software โ so systems can update, optimize, and sustain themselves over time.
What this means in practice is a combination of:
โข ๐๐บ๐ฏ๐ฒ๐ฑ๐ฑ๐ฒ๐ฑ ๐ฝ๐ฟ๐ผ๐ฐ๐ฒ๐๐๐ผ๐ฟ & ๐๐ช/๐ฆ๐ช ๐ฐ๐ผ-๐ฑ๐ฒ๐๐ถ๐ด๐ป: from microarchitectures and memory hierarchies to operating systems, runtimes, and RTL โ bridging algorithms to silicon.
โข ๐๐๐ป๐ฎ๐บ๐ถ๐ฐ ๐ฃ๐ฎ๐ฟ๐๐ถ๐ฎ๐น ๐ฅ๐ฒ๐ฐ๐ผ๐ป๐ณ๐ถ๐ด๐๐ฟ๐ฎ๐๐ถ๐ผ๐ป (๐๐ฃ๐ฅ): hardware that can change at runtime to fit the task.
โข ๐ฒ๐๐ฃ๐๐-๐ฒ๐ป๐ต๐ฎ๐ป๐ฐ๐ฒ๐ฑ ๐ฆ๐ผ๐๐: tightly-coupled designs where we add domain-specific (instruction) extensions to processors on demand, utilizing embedded FPGAs (eFPGAs).
โข ๐ฅ๐๐ฆ๐-๐ฉ & ๐ผ๐ฝ๐ฒ๐ป ๐ฒ๐ฐ๐ผ๐๐๐๐๐ฒ๐บ๐: open ISA, open tooling, and Open Educational Resources (OER) in teaching.
โข ๐๐-๐ฎ๐๐ด๐บ๐ฒ๐ป๐๐ฒ๐ฑ & ๐๐๐๐๐ฎ๐ถ๐ป๐ฎ๐ฏ๐น๐ฒ ๐ฑ๐ถ๐ด๐ถ๐๐ฎ๐น ๐๐๐๐๐ฒ๐บ ๐ฑ๐ฒ๐๐ถ๐ด๐ป: faster design cycles, lower resource usage, and longer device lifetimes โ ultimately reducing e-waste.
In teaching, Iโll keep pushing ๐ต๐ฎ๐ป๐ฑ๐-๐ผ๐ป, ๐ฝ๐ฟ๐ผ๐ท๐ฒ๐ฐ๐-๐ฏ๐ฎ๐๐ฒ๐ฑ ๐น๐ฒ๐ฎ๐ฟ๐ป๐ถ๐ป๐ด โ from C and embedded systems to reconfigurable SoC design โ because the best way to learn systems is to build them.
Iโm grateful to all mentors, collaborators, and students whoโve shaped this journey. Looking ahead, Iโm excited to deepen our ties with the ๐น๐ผ๐ฐ๐ฎ๐น ๐๐ฒ๐บ๐ถ๐ฐ๐ผ๐ป๐ฑ๐๐ฐ๐๐ผ๐ฟ ๐ถ๐ป๐ฑ๐๐๐๐ฟ๐, grow open-source design flows (and add a few tapeouts into the mix!), and co-create impactful RCA research with industry and academic partners.
If youโre a ๐๐๐๐ฑ๐ฒ๐ป๐ curious about projects or theses, or an ๐ถ๐ป๐ฑ๐๐๐๐ฟ๐ ๐ผ๐ฟ ๐ฎ๐ฐ๐ฎ๐ฑ๐ฒ๐บ๐ถ๐ฐ ๐ฐ๐ผ๐น๐น๐ฒ๐ฎ๐ด๐๐ฒ interested in collaboration, letโs talk.
Read the original article on LinkedIn.