Tenure Track unlocked.

Iโ€™m happy to announce that Iโ€™m starting as a ๐—ง๐—ฒ๐—ป๐˜‚๐—ฟ๐—ฒ-๐—ง๐—ฟ๐—ฎ๐—ฐ๐—ธ ๐—”๐˜€๐˜€๐—ถ๐˜€๐˜๐—ฎ๐—ป๐˜ ๐—ฃ๐—ฟ๐—ผ๐—ณ๐—ฒ๐˜€๐˜€๐—ผ๐—ฟ ๐—ผ๐—ณ ๐—ฅ๐—ฒ๐—ฐ๐—ผ๐—ป๐—ณ๐—ถ๐—ด๐˜‚๐—ฟ๐—ฎ๐—ฏ๐—น๐—ฒ ๐—–๐—ผ๐—บ๐—ฝ๐˜‚๐˜๐—ฒ๐—ฟ ๐—”๐—ฟ๐—ฐ๐—ต๐—ถ๐˜๐—ฒ๐—ฐ๐˜๐˜‚๐—ฟ๐—ฒ๐˜€ (๐—ฅ๐—–๐—”) at Technische Universitรคt Graz. ๐Ÿš€

RCA is about making hardware as ๐˜ข๐˜ฅ๐˜ข๐˜ฑ๐˜ต๐˜ข๐˜ฃ๐˜ญ๐˜ฆ as software โ€“ so systems can update, optimize, and sustain themselves over time.

What this means in practice is a combination of:
 โ€ข ๐—˜๐—บ๐—ฏ๐—ฒ๐—ฑ๐—ฑ๐—ฒ๐—ฑ ๐—ฝ๐—ฟ๐—ผ๐—ฐ๐—ฒ๐˜€๐˜€๐—ผ๐—ฟ & ๐—›๐—ช/๐—ฆ๐—ช ๐—ฐ๐—ผ-๐—ฑ๐—ฒ๐˜€๐—ถ๐—ด๐—ป: from microarchitectures and memory hierarchies to operating systems, runtimes, and RTL โ€“ bridging algorithms to silicon.
 โ€ข ๐——๐˜†๐—ป๐—ฎ๐—บ๐—ถ๐—ฐ ๐—ฃ๐—ฎ๐—ฟ๐˜๐—ถ๐—ฎ๐—น ๐—ฅ๐—ฒ๐—ฐ๐—ผ๐—ป๐—ณ๐—ถ๐—ด๐˜‚๐—ฟ๐—ฎ๐˜๐—ถ๐—ผ๐—ป (๐——๐—ฃ๐—ฅ): hardware that can change at runtime to fit the task.
 โ€ข ๐—ฒ๐—™๐—ฃ๐—š๐—”-๐—ฒ๐—ป๐—ต๐—ฎ๐—ป๐—ฐ๐—ฒ๐—ฑ ๐—ฆ๐—ผ๐—–๐˜€: tightly-coupled designs where we add domain-specific (instruction) extensions to processors on demand, utilizing embedded FPGAs (eFPGAs).
 โ€ข ๐—ฅ๐—œ๐—ฆ๐—–-๐—ฉ & ๐—ผ๐—ฝ๐—ฒ๐—ป ๐—ฒ๐—ฐ๐—ผ๐˜€๐˜†๐˜€๐˜๐—ฒ๐—บ๐˜€: open ISA, open tooling, and Open Educational Resources (OER) in teaching.
 โ€ข ๐—”๐—œ-๐—ฎ๐˜‚๐—ด๐—บ๐—ฒ๐—ป๐˜๐—ฒ๐—ฑ & ๐˜€๐˜‚๐˜€๐˜๐—ฎ๐—ถ๐—ป๐—ฎ๐—ฏ๐—น๐—ฒ ๐—ฑ๐—ถ๐—ด๐—ถ๐˜๐—ฎ๐—น ๐˜€๐˜†๐˜€๐˜๐—ฒ๐—บ ๐—ฑ๐—ฒ๐˜€๐—ถ๐—ด๐—ป: faster design cycles, lower resource usage, and longer device lifetimes โ€“ ultimately reducing e-waste.

In teaching, Iโ€™ll keep pushing ๐—ต๐—ฎ๐—ป๐—ฑ๐˜€-๐—ผ๐—ป, ๐—ฝ๐—ฟ๐—ผ๐—ท๐—ฒ๐—ฐ๐˜-๐—ฏ๐—ฎ๐˜€๐—ฒ๐—ฑ ๐—น๐—ฒ๐—ฎ๐—ฟ๐—ป๐—ถ๐—ป๐—ด โ€“ from C and embedded systems to reconfigurable SoC design โ€“ because the best way to learn systems is to build them.

Iโ€™m grateful to all mentors, collaborators, and students whoโ€™ve shaped this journey. Looking ahead, Iโ€™m excited to deepen our ties with the ๐—น๐—ผ๐—ฐ๐—ฎ๐—น ๐˜€๐—ฒ๐—บ๐—ถ๐—ฐ๐—ผ๐—ป๐—ฑ๐˜‚๐—ฐ๐˜๐—ผ๐—ฟ ๐—ถ๐—ป๐—ฑ๐˜‚๐˜€๐˜๐—ฟ๐˜†, grow open-source design flows (and add a few tapeouts into the mix!), and co-create impactful RCA research with industry and academic partners.

If youโ€™re a ๐˜€๐˜๐˜‚๐—ฑ๐—ฒ๐—ป๐˜ curious about projects or theses, or an ๐—ถ๐—ป๐—ฑ๐˜‚๐˜€๐˜๐—ฟ๐˜† ๐—ผ๐—ฟ ๐—ฎ๐—ฐ๐—ฎ๐—ฑ๐—ฒ๐—บ๐—ถ๐—ฐ ๐—ฐ๐—ผ๐—น๐—น๐—ฒ๐—ฎ๐—ด๐˜‚๐—ฒ interested in collaboration, letโ€™s talk.

Read the original article on LinkedIn.

Tobias Scheipel

I am a postdoctoral researcher and teacher at the Embedded Architectures & Systems Group at the Institute of Technical Informatics, Graz University of Technology. I conducted my PhD under the supervision of Prof. Marcel Baunach and graduated sub auspiciis Praesidentis rei publicae. You can find my dissertation here.

My research focuses on flexible and runtime-reconfigurable FPGA-based microcontroller architectures for embedded systems based on RISC-V. This involves hardware/software codesign strategies for both processor logic and embedded operating systems.

Apart from my research, I teach students how a CPU works, how to program embedded systems, how to write scientific publications, and how to create their own CPU.