Showing 3 Result(s)

Tenure Track unlocked.

Iโ€™m happy to announce that Iโ€™m starting as a ๐—ง๐—ฒ๐—ป๐˜‚๐—ฟ๐—ฒ-๐—ง๐—ฟ๐—ฎ๐—ฐ๐—ธ ๐—”๐˜€๐˜€๐—ถ๐˜€๐˜๐—ฎ๐—ป๐˜ ๐—ฃ๐—ฟ๐—ผ๐—ณ๐—ฒ๐˜€๐˜€๐—ผ๐—ฟ ๐—ผ๐—ณ ๐—ฅ๐—ฒ๐—ฐ๐—ผ๐—ป๐—ณ๐—ถ๐—ด๐˜‚๐—ฟ๐—ฎ๐—ฏ๐—น๐—ฒ ๐—–๐—ผ๐—บ๐—ฝ๐˜‚๐˜๐—ฒ๐—ฟ ๐—”๐—ฟ๐—ฐ๐—ต๐—ถ๐˜๐—ฒ๐—ฐ๐˜๐˜‚๐—ฟ๐—ฒ๐˜€ (๐—ฅ๐—–๐—”) at Technische Universitรคt Graz. ๐Ÿš€ RCA is about making hardware as ๐˜ข๐˜ฅ๐˜ข๐˜ฑ๐˜ต๐˜ข๐˜ฃ๐˜ญ๐˜ฆ as software โ€“ so systems can update, optimize, and sustain themselves over time. What this means in practice is a combination of: โ€ข ๐—˜๐—บ๐—ฏ๐—ฒ๐—ฑ๐—ฑ๐—ฒ๐—ฑ ๐—ฝ๐—ฟ๐—ผ๐—ฐ๐—ฒ๐˜€๐˜€๐—ผ๐—ฟ & ๐—›๐—ช/๐—ฆ๐—ช ๐—ฐ๐—ผ-๐—ฑ๐—ฒ๐˜€๐—ถ๐—ด๐—ป: from microarchitectures and memory hierarchies to operating systems, runtimes, and RTL โ€“ bridging algorithms to silicon. โ€ข ๐——๐˜†๐—ป๐—ฎ๐—บ๐—ถ๐—ฐ ๐—ฃ๐—ฎ๐—ฟ๐˜๐—ถ๐—ฎ๐—น ๐—ฅ๐—ฒ๐—ฐ๐—ผ๐—ป๐—ณ๐—ถ๐—ด๐˜‚๐—ฟ๐—ฎ๐˜๐—ถ๐—ผ๐—ป (๐——๐—ฃ๐—ฅ): hardware that can change at runtime to fit the task. โ€ข ๐—ฒ๐—™๐—ฃ๐—š๐—”-๐—ฒ๐—ป๐—ต๐—ฎ๐—ป๐—ฐ๐—ฒ๐—ฑ ๐—ฆ๐—ผ๐—–๐˜€: tightly-coupled designs where we add domain-specific (instruction) extensions to processors on demand, …

HaDes-V Launch

We are thrilled to announce the kickoff of our newly designed, RISC-V-based Microcontroller Design, Lab! This year marks the first iteration of the new format, where students will embark on a hands-on learning experience as they delve into implementing the all-new RISC-V-based HaDes-V architecture. Special thanks to David Beikircher and Florian Riedl for implementing the course. Link to original LinkedIn post